The increasing operating speeds and computing power of microelectronic devices have recently given rise to the need for an increase in the complexity and functionality of the semiconductor structures that are used as the starting substrates in these microelectronic devices. Such “virtual substrates” based on silicon and germanium provide a platform for new generations of very large scale integration (“VLSI”) devices that exhibit enhanced performance when compared to devices fabricated on bulk Si substrates. Specifically, new technological advances enable formation of heterostructures using silicon-germanium alloys (hereinafter referred to as “SiGe” or “Si1-xGex”) to further increase performance of the semiconductor devices by changing the atomic structure of Si to increase electron and hole mobility.
The important component of a SiGe virtual substrate is a layer of SiGe heterostructure that has been relaxed to its equilibrium lattice constant (i.e., one that is larger than that of Si). This relaxed SiGe layer can be directly applied to a Si substrate (e.g., by wafer bonding or direct epitaxy), or atop a relaxed graded SiGe buffer layer in which the lattice constant of the SiGe material has been increased gradually over the thickness of the layer. The SiGe virtual substrate may also incorporate buried insulating layers, in the manner of a silicon-on-insulator (SOI) wafer. To fabricate high-performance devices on these platforms, thin strained layers of semiconductors, such as Si, Ge, or SiGe, are grown on the relaxed SiGe virtual substrates. The resulting biaxial tensile or compressive strain alters the carrier mobilities in the layers, enabling the fabrication of high-speed and/or low-power-consumption devices. The percentage of Ge in SiGe and the method of deposition can have a dramatic effect on the characteristics of the strained Si layer. U.S. Pat. No. 5,442,205, “Semiconductor Heterostructure Devices with Strained Semiconductor Layers,” incorporated herein by reference, describes one such method of producing a strained Si device structure.
An approach to epitaxially growing a relaxed SiGe layer on bulk Si is discussed in International Application Publication No. WO 01/22482, entitled “Method of Producing Relaxed Silicon Germanium Layers” and incorporated herein by reference. The method includes providing a monocrystalline Si substrate, and then epitaxially growing a graded Si1-xGex layer with increasing Ge concentration at a gradient of less than 25% Ge per micrometer to a final Ge composition in the range of 0.1<x<1, using a source gas of GexHyClz for the Ge component, on the Si substrate at a temperature in excess of 850° C., and then epitaxially growing a semiconductor material on the graded layer.
Another method of epitaxially growing a relaxed SiGe layer on bulk Si is discussed in a paper entitled, “Low Energy plasma enhanced chemical vapor deposition,” by M. Kummer et al. (Mat. Sci. & Eng. B89, 2002, pp. 288–95) and incorporated herein by reference, in which a method of low-energy plasma-enhanced chemical vapor deposition (LEPECVD) is disclosed. This method allows the formation of a SiGe layer on bulk Si at high growth rates (0.6 μm per minute) and low temperatures (500–750° C.).
To grow a high-quality, thin, epitaxial strained Si layer on a graded SiGe layer, the SiGe layer is, preferably, planarized or smoothed to reduce the surface roughness in the final strained Si substrate. Current methods of chemical mechanical polishing (“CMP”) are typically used to decrease roughness and improve the planarity of surfaces in semiconductor fabrication processes. U.S. Pat. No. 6,107,653, “Controlling Threading Dislocations in Ge on Si Using Graded GeSi Layers and Planarization,” incorporated herein by reference, describes how planarization can be used to improve the quality of SiGe graded layers.
One technique suitable for fabricating strained Si wafers can include the following steps:                1. Providing a silicon substrate that has been edge-polished;        2. Epitaxially depositing a relaxed graded SiGe buffer layer to a final Ge composition on the silicon substrate;        3. Epitaxially depositing a relaxed Si1-xGex cap layer having a constant composition on the graded SiGe buffer layer;        4. Planarizing or smoothing the Si1-xGex cap layer and/or the relaxed graded SiGe buffer layer by, e.g., CMP;        5. Epitaxially depositing a relaxed Si1-xGex regrowth layer having a constant composition on the planarized surface of the Si1-xGex cap layer; and        6. Epitaxially depositing a strained silicon layer on the Si1-xGex regrowth layer.        
By introducing strain gradually over a series of low lattice mismatch interfaces, compositionally graded layers, as recited in step 2 above, offer a viable route toward integration of heavily lattice-mismatched monocrystalline semiconductor layers on a common substrate, offering a route towards increased functionality through monolithic integration. Utilizing both strain and bandgap engineering, modulation-doped FETs (MODFETs) and metal-oxide-semiconductor FETs (MOSFETs) may be tailored for enhanced-performance analog or digital applications. However, because these devices are fabricated on Si/SiGe virtual substrates rather than on the Si substrates commonly utilized for complementary MOS (CMOS) technologies, they present new processing challenges.
For example, because thin, near-surface, strained heteroepitaxial layers constitute critical parts of devices formed on relaxed SiGe virtual substrates the processing windows for such structures are limited. Specifically, it is desirable to avoid the consumption of these near-surface strained layers during processing. Traditional silicon-based CMOS process flows, therefore, may not be suitable for these layers because conventional CMOS processes typically result in the consumption of a large portion of surface substrate material. This consumption is primarily due to thermal oxidation steps. For example, thin thermally grown oxides are commonly used as screening layers (also called “passivation layers”) during ion implantation steps. These passivation layers also serve to discourage out-diffusion of dopants during subsequent thermal anneals. Also, thermally grown pad oxides are used as a stress-mediating underlayer beneath a silicon nitride trench mask layer for shallow trench isolation (STI) formation. These thermal oxidation steps, however, typically remove a total of several hundred angstroms (Å) of surface Si material. Accordingly, thermal oxidation is not desirable when processing wafers that incorporate thin surface layers formed on SiGe virtual substrates, where a final minimum thickness of 50 Å of the thin strained layer (from a starting thickness of, e.g., 50–200 Å) needs to be available for device channels.
Thus, there is a need in the art for method for forming a semiconductor structure that minimizes consumption of the material proximate to the top surface of the substrate.